1. Field of the Invention
This invention relates to a method and a hardware arrangement for controlling memory bank access requests made by arithmetic and/or input/output processors in a data processing system, and more specifically to such a method and an arrangement in which memory banks are accessible regardless of the order of request reception and in which competing access requests for the same memory bank can be settled effectively by way of a simple circuit configuration.
2. Description of the Prior Art
A main memory of a computer may take a form of an arrangement comprising a plurality of banks which are independently accessible by arithmetic and input/output processors. In order to attain the desired high overall operative performance of a computer having such a main memory, it is vital to process bank access requests regardless of the order of reception thereof. This means that accesses which compete for the same bank must be treated effectively.
To this end, memory bank access techniques for controlling competition for the same bank is disclosed in Japanese Patent Application No. 49-142917 filed Dec. 12, 1974 and is laid open Jun. 14, 1976 under the provisional publication No. 51-68735.
This prior art generally comprises: a shift register assembly which includes a plurality of storage units or registers coupled in series; a bank state indicator which provides information indicating whether or not each of memory banks of a main memory is available; a plurality of bank access decision circuits all of which are respectively coupled to the associated storage units of the shift register assembly for receiving the outputs therefrom; and a priority decision circuit which receives all of the outputs of the bank access decision circuits.
According to this prior art, bank access requests are sequentially applied to the shift register assembly and are moved from one register to another under the control of system clocks. Each of the bank access decision circuits, receives the bank state information and the output of the associated storage unit of the shift register assembly. In the event that competition of access requests for the same bank occurs, the priority decision circuit selects one bank access request which is stored in a lower storage unit provided in the lowest position among the storage units containing the competing requests.
The above-mentioned prior art is provided with a number of bank access decision circuits which may simultaneously apply a number of access requests to the priority decision circuit. It follows that the priority decision circuit must select one from a number of requests applied at the same time. Consequently, the prior art is complex in circuit configuration and is especially sophisticated in selecting one access request in preference of the other competing request(s). Further, this prior art is unsuitable for fabrication into an integrated circuit due to its bulky and complicated arrangement.